DFT (Design for Testability) Pattern Generation Task for Circuit Under Test
نویسندگان
چکیده
In this paper, we will present a method to reduce the power consumption during testing of a circuit-under-test (CUT). In proposed scheme the power reduced in two steps. In first step power reduced using gated clock design approach and in second step reduces the no of reduces the number of transitions at the inputs of the circuit-under-test. KeywordsLFSR, Clock gating, Bit swapping, Bilt-in-self-test
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تاریخ انتشار 2011